74LVC07A Low-Voltage CMOS Hex Buffer with Open Drain Outputs With 5 V Tolerant Inputs www.onsemi.com The 74LVC07A is a high performance hex buffer operating from a 1.2 V to 5.5 V supply. High impedance TTL compatible inputs MARKING significantly reduce current loading to input drivers. These LVC DIAGRAMS devices have open drain outputs which provide the ability to set output levels, or do activeHIGH AND or activeLOW OR functions. A V I 14 specification of 5.5 V allows 74LVC07A inputs to be safely driven SOIC14 LVC07AG from 5.0 V devices. 14 D SUFFIX AWLYWW CASE 751A 1 Features 1 Designed for 1.2 V to 5.5 V V Operation CC 5.0 V Tolerant Inputs/Outputs 14 LVTTL Compatible LVCMOS Compatible LVC TSSOP14 24 mA Output Sink Capability 14 07A DT SUFFIX CASE 948G ALYW Near Zero Static Supply Current (10 A) Substantially Reduces 1 System Power Requirements Latchup Performance Exceeds 250 mA 1 WiredOR, WiredAND A = Assembly Location Output Level Can Be Set Externally Without Affecting Speed of WL, L = Wafer Lot Device Y = Year WW, W = Work Week ESD Performance: Human Body Model >2000 V G or = PbFree Package Machine Model >200 V (Note: Microdot may be in either location) These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION V A3 O3 A4 O4 A5 O5 CC See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 14 13 12 11 10 9 8 1 2 3 4 567 A0 O0 A1 O1 A2 O2 GND Figure 1. Pinout: 14Lead (Top View) Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: December, 2015 Rev. 0 74LVC07A/D74LVC07A 1 2 * Table 1. PIN NAMES A0 O0 Pins Function 3 4 * A1 O1 An Data Inputs On Outputs 5 6 * A2 O2 13 12 * A3 O3 Table 2. TRUTH TABLE An On 11 10 * A4 O4 L L H Z 9 8 * A5 O5 * OD Figure 2. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Condition Unit V DC Supply Voltage 0.5 to +6.5 V CC V DC Input Voltage 0.5 V +6.5 V I I V DC Output Voltage 0.5 V +6.5 Output in 3State V O O 0.5 V V + 0.5 Output in HIGH or LOW State (Note 1) O CC I DC Input Diode Current 50 V < GND mA IK I I DC Output Diode Current 50 V < GND mA OK O +50 V > V mA O CC I DC Output Source/Sink Current 50 mA O I DC Supply Current Per Supply Pin 100 mA CC I DC Ground Current Per Ground Pin 100 mA GND T Storage Temperature Range 65 to +150 C STG T Lead Temperature, 1 mm from Case for T = 260 C L L 10 Seconds T Junction Temperature Under Bias T = 135 C J J Thermal Resistance (Note 2) SOIC = 85 C/W JA TSSOP = 100 MSL Moisture Sensitivity Level 1 I Latchup Performance at V = 3.6 V 250 mA LATCHUP CC and 125C (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. I absolute maximum rating must be observed. O 2. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 2 ounce copper trace no air flow. 3. Tested to EIA/JES078. ORDERING INFORMATION Device Package Shipping 74LVC07ADR2G SOIC14 2500 / Tape & Reel (PbFree) 74LVC07ADTR2G TSSOP14 2500 / Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2