74LVC163PW/TSSOP16 Nexperia

74LVC163 Presettable synchronous 4-bit binary counter synchronous reset Rev. 6 20 November 2012 Product data sheet 1. General description The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by t PHL (propagation delay CP to TC) and t (set-up time CEP to CP) according to the formula: su 1 . f = ----------------------------------- max t +t PHLmax su 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Synchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V)74LVC163 NXP Semiconductors Presettable synchronous 4-bit binary counter synchronous reset JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to 125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC163D 40 Cto +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC163DB 40 Cto +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74LVC163PW 40 Cto +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC163BQ 40 Cto +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram 1 CTR4 R 9 15 M1 7 G3 TC 10 G4 3 D0 Q0 14 2 C2/1,3,4+ 13 4 D1 Q1 14 3 1,2D 5 D2 Q2 12 13 4 6 D3 Q3 11 5 12 9 PE 6 11 CEP CET CP MR 15 4 CT = 15 mna905 7 10 2 1 mna906 Fig 1. Logic diagram Fig 2. IEC logic symbol 74LVC163 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 20 November 2012 2 of 20