74LVC1G08GW-Q100,1 Nexperia

74LVC1G08-Q100 Single 2-input AND gate Rev. 2 7 December 2016 Product data sheet 1. General description The 74LVC1G08-Q100 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )74LVC1G08-Q100 Nexperia Single 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC1G08GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74LVC1G08GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 4. Marking Table 2. Marking 1 Type number Marking code 74LVC1G08GW-Q100 VE 74LVC1G08GV-Q100 V08 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram % < < % D PQ QD P D PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 9& * 4 / % 9 *1 < DDD Fig 4. Pin configuration SOT353-1 and SOT753 74LVC1G08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 7 December 2016 2 of 13 &&