74LVC1G10GW-Q100H Nexperia

74LVC1G10-Q100 Single 3-input NAND gate Rev. 3 2 June 2021 Product data sheet 1. General description The 74LVC1G10-Q100 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G10GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363Nexperia 74LVC1G10-Q100 Single 3-input NAND gate 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G10GW YM 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 A A 3 4 B Y B Y 1 & 6 C 3 4 6 C 001aag688 001aag686 001aag687 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G10 A 1 6 C GND 2 5 V CC B 3 4 Y 001aag689 Fig. 4. Pin configuration SOT363 (SC-88) 6.2. Pin description Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) B 3 data input Y 4 data output V 5 supply voltage CC C 6 data input 74LVC1G10 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 2 June 2021 2 / 10