74LVC1G157GW,125 Nexperia

74LVC1G157 Single 2-input multiplexer Rev. 10 10 June 2021 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V I circuitry provides partial Power-down mode operation OFF ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G157GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC1G157GV -40 C to +125 C SC-74 plastic surface-mounted package 6 leads SOT457 TSOP6 74LVC1G157GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74LVC1G157GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVC1G157GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74LVC1G157 Single 2-input multiplexer 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G157GW YP 74LVC1G157GV YP 74LVC1G157GM YP 74LVC1G157GN YP 74LVC1G157GS YP 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 3 6 G1 I1 I0 6 S 3 1 MUX Y 4 1 1 4 001aac652 001aac653 Fig. 1. Logic symbol Fig. 2. IEC logic symbol S 1 I1 4 MULTIPLEXER SELECTOR Y 3 I1 OUTPUT S I0 Y 6 I0 001aac655 S 001aac654 Fig. 3. Functional diagram Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G157 74LVC1G157 I1 1 6 S I1 1 6 S 74LVC1G157 I1 1 6 S 2 5 GND 2 5 V GND V CC CC GND 2 5 V CC I0 3 4 Y I0 3 4 Y I0 3 4 Y 001aac657 001aaf545 001aac656 Transparent top view Transparent top view Fig. 5. Pin configuration SOT363 (SC-88) and Fig. 6. Pin configuration Fig. 7. Pin configuration SOT1115 SOT457 (SC-74 TSOP6) SOT886 (XSON6) and SOT1202 (XSON6) 74LVC1G157 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 10 June 2021 2 / 14