74LVC1G175GM NXP

74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Rev. 7 2 December 2016 Product data sheet 1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V). ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C.74LVC1G175 Nexperia Single D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G175GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G175GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G175GM 40 C to +125 C XSON6 plastic extremely thin small outline package; SOT886 no leads; 6 terminals; body 1 1.45 0.5 mm 74LVC1G175GF 40 C to +125 C XSON6 plastic extremely thin small outline package; SOT891 no leads; 6 terminals; body 1 1 0.5 mm 74LVC1G175GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 1.0 0.35 mm 74LVC1G175GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking [1] Type number Marking code 74LVC1G175GW YT 74LVC1G175GV V75 74LVC1G175GM YT 74LVC1G175GF YT 74LVC1G175GN YT 74LVC1G175GS YT [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram    '  ))  4  '4   05 DDD Fig 1. Logic symbol. Fig 2. IEC logic symbol. 74LVC1G175 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 2 December 2016 2 of 20 DDD &3 &3 05