74LVC377 Octal D-type flip-flop with data enable positive-edge trigger Rev. 7 27 August 2021 Product data sheet 1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC377D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC377PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mmNexperia 74LVC377 Octal D-type flip-flop with data enable positive-edge trigger 4. Functional diagram 11 1C2 1 G1 11 3 2 CP 2D 3 2 D0 Q0 4 5 4 5 D1 Q1 7 6 7 6 D2 Q2 8 9 8 9 D3 Q3 13 12 13 12 D4 Q4 14 15 D5 Q5 14 15 17 16 D6 Q6 17 16 18 19 D7 Q7 18 19 E 1 mna918 mna919 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVC377 E 1 20 V CC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP mna917 Fig. 3. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) 5.2. Pin description Table 2. Pin description Symbol Pin Description E 1 data enable input (active LOW) CP 11 clock input (LOW to HIGH edge-triggered) D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output GND 10 ground (0 V) V 20 power supply CC 74LVC377 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 27 August 2021 2 / 12