74LVC3G04DP,125 Nexperia

74LVC3G04 Triple inverter Rev. 14 16 April 2021 Product data sheet 1. General description The 74LVC3G04 is a triple inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3G04DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC3G04DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74LVC3G04GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74LVC3G04GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74LVC3G04GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mmNexperia 74LVC3G04 Triple inverter 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC3G04DP V04 74LVC3G04DC V04 74LVC3G04GT V04 74LVC3G04GN V4 74LVC3G04GS V4 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1 2A 2Y 1 3A 3Y A Y 001aah793 001aah794 mna110 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one driver) 6. Pinning information 6.1. Pinning 74LVC3G04 1A 1 8 V CC 3Y 2 7 1Y 74LVC3G04 2A 3 6 3A 1 8 1A V CC 3Y 2 7 1Y GND 4 5 2Y 2A 3 6 3A 5 GND 4 2Y 001aad955 001aad954 Transparent top view Fig. 4. Pin configuration SOT505-2 (TSSOP8) and Fig. 5. Pin configuration SOT833-1, SOT1116 and SOT765-1 (VSSOP8) SOT1203 (XSON8) 74LVC3G04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 14 16 April 2021 2 / 15