IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIP- FLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16374A 16-bit edge-triggered D-type register is built using Typical tSK(o) (Output Skew) < 250ps advanced dual metal CMOS technology. This high-speed, low-power ESD > 2000V per MIL-STD-883, Method 3015 > 200V using register is ideal for use as a buffer register for data synchronization and machine model (C = 200pF, R = 0) storage. The Output Enable (OE) and clock (CLK) controls are organized VCC = 3.3V 0.3V, Normal Range to operate each device as two 8-bit registers or one 16-bit register with VCC = 2.7V to 3.6V, Extended Range common clock. Flow-through organization of signal pins simplifies layout. All CMOS power levels (0.4 W typ. static) inputs are designed with hysteresis for improved noise margin. All inputs, outputs, and I/O are 5V tolerant All pins of the LVCH16374A can be driven from either 3.3V or 5V devices. Supports hot insertion This feature allows the use of this device as a translator in a mixed 3.3V/5V Available in SSOP and TSSOP packages supply system. The LVCH16374A has been designed with a 24mA output driver. This DRIVE FEATURES: driver is capable of driving a moderate to heavy load while maintaining High Output Drivers: 24mA speed performance. Reduced system switching noise The LVCH16374A has bus-hold which retains the inputs last state whenever the input goes to a high impedance. This prevents floating inputs APPLICATIONS: and eliminates the need for pull-up/down resistors. 5V and 3.3V mixed voltage systems Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 24 1OE 2OE 48 25 2CLK 1CLK C1 C1 2 13 47 36 1D 1D 1Q1 2D1 2Q1 1D1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 2015 1 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4643/5IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V 1CLK 1OE 1 48 TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 mA 1D1 2 1Q1 47 IIK Continuous Clamp Current, 50 mA 1D2 1Q2 3 46 IOK VI < 0 or VO < 0 GND 4 45 GND ICC Continuous Current through each 100 mA ISS VCC or GND 5 1D3 1Q3 44 NOTE: 6 1D4 1Q4 43 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation VCC 7 VCC 42 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 8 1D5 1Q5 41 conditions for extended periods may affect reliability. 1D6 9 40 1Q6 GND 10 GND 39 1D7 11 38 1Q7 CAPACITANCE (TA = +25C, F = 1.0MHz) 12 1D8 1Q8 37 (1) Symbol Parameter Conditions Typ. Max. Unit 13 2D1 2Q1 36 CIN Input Capacitance VIN = 0V 4.5 6 pF 2D2 14 2Q2 35 COUT Output Capacitance VOUT = 0V 6.5 8 pF GND GND 15 34 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 16 NOTE: 33 2D3 2Q3 1. As applicable to the device type. 17 32 2D4 2Q4 18 31 VCC VCC 19 30 2D5 2Q5 PIN DESCRIPTION 20 2D6 29 2Q6 Pin Names Description 21 GND GND 28 (1) xDx Data Inputs 22 2D7 27 2Q7 xCLK Clock Inputs 23 2D8 xOE Output Enable Inputs (Active LOW) 2Q8 26 x Q x 3-State Outputs 24 2CLK 2OE 25 NOTE: 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. SSOP / TSSOP TOP VIEW (1) FUNCTION TABLE (EACH FLIP-FLOP) Inputs Outputs xDx xCLK xOE xQx H LH L LL (2) X H or L L Q XX H Z NOTES: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High-Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2