IDT74LVCH16543A INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3.3V CMOS 16-BIT IDT74LVCH16543A REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION FEATURES: Typical tSK(o) (Output Skew) < 250ps The LVCH16543A 16-bit registered transceiver is built using advanced ESD > 2000V per MIL-STD-883, Method 3015 > 200V using dual metal CMOS technology. The LVCH16543A can be used as two 8-bit machine model (C = 200pF, R = 0) transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or VCC = 3.3V 0.3V, Normal Range LEBA) and output-enable (OEAB or OEBA) inputs are provided for each VCC = 2.7V to 3.6V, Extended Range register to permit independent control in either direction of data flow. The CMOS power levels (0.4 W typ. static) A-to-B enable (CEAB) input must be low in order to enter data from the A All inputs, outputs, and I/O are 5V tolerant port or to output data from the B port. LEAB controls the latch function. When Supports hot insertion LEAB is low, the A to B latches are transparent. A subsequent low-to-high Available in TSSOP package transition of LEAB puts the A latches in the storage mode. OEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using CEBA, LEBA, and OEBA inputs. Flow-through DRIVE FEATURES: organization of signal pins simplifies layout. All inputs are designed with High Output Drivers: 24mA hysteresis for improved noise margin. Reduced system switching noise All pins of this 16-bit registered transceiver can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in APPLICATIONS: a mixed 3.3V/5V supply system. 5V and 3.3V mixed voltage systems The LVCH16543A has been designed with a 24mA output driver. This Data communication and telecommunication systems driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16543A has bus-hold which retains the inputs last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM 29 56 2OEBA 1OEBA 31 54 2CEBA 1CEBA 30 55 1LEBA 2LEBA 28 1 2OEAB 1OEAB 3 26 1CEAB 2CEAB 2 27 1LEAB 2LEAB C1 C1 15 5 2A1 1A1 42 52 2B1 1D 1B1 1D C1 C1 1D 1D TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2016 1 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4612/6IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V 1 56 1OEAB 1OEBA TSTG Storage Temperature 65 to +150 C 2 55 1LEAB 1LEBA IOUT DC Output Current 50 to +50 mA IIK Continuous Clamp Current, 50 mA 1CEAB 3 54 1CEBA IOK VI < 0 or VO < 0 GND 4 53 GND ICC Continuous Current through each 100 mA 5 ISS VCC or GND 1A1 52 1B1 6 1A2 NOTE: 1B2 51 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause VCC 7 VCC 50 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 1A3 8 49 1B3 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9 48 1A4 1B4 10 1A5 47 1B5 11 46 GND GND 1A6 12 45 1B6 PIN DESCRIPTION 1A7 13 44 1B7 Pin Names Description 1A8 14 1B8 43 xOEAB A-to-B Output Enable Input (Active LOW) 15 xOEBA B-to-A Output Enable Input (Active LOW) 2A1 42 2B1 xCEAB A-to-B Enable Input (Active LOW) 2A2 16 2B2 41 xCEBA B-to-A Enable Input (Active LOW) 2A3 17 2B3 40 xLEAB A-to-B Latch Enable Input (Active LOW) 18 GND 39 GND xLEBA B-to-A Latch Enable Input (Active LOW) (1) 19 38 2A4 x A x A-to-B Data Inputs or B-to-A 3-State Outputs 2B4 (1) x B x B-to-A Data Inputs or A-to-B 3-State Outputs 2A5 20 37 2B5 NOTE: 2A6 21 36 2B6 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. CC V 22 VCC 35 2A7 23 2B7 34 2A8 (1,2) 24 2B8 33 FUNCTION TABLE (EACH 8-BIT SECTION) GND 25 Inputs Latch Status Output Buffers 32 GND 26 2CEBA xCEAB xLEAB xOEAB xAx to xBx xBx 2CEAB 31 27 2LEBA H X X Storing High Z 2LEAB 30 X X H Storing High Z 28 2OEAB 2OEBA 29 L L L Transparent Current A Inputs (3) L H L Storing Previous A Inputs TSSOP L L H Transparent High Z TOP VIEW L H H Storing High Z X H X Storing Not Recommended NOTES: CAPACITANCE (TA = +25C, F = 1.0MHz) 1. H = HIGH Voltage Level (1) Symbol Parameter Conditions Typ. Max. Unit L = LOW Voltage Level X = Dont Care CIN Input Capacitance VIN = 0V 4.5 6 pF Z = High-Impedance COUT Output Capacitance VOUT = 0V 6.5 8 pF 2. A-to-B data flow is shown. B-to-A data flow is similar but uses xCEBA, xLEBA, and xOEBA. CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 3. Before xLEAB LOW-to-HIGH transition. NOTE: 1. As applicable to the device type. 2