DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking Description function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, This 28-bit 1:2 registered buffer with parity is designed for compares it with the data received on the D-inputs and 1.7V to 1.9V VDD operation. indicates whether a parity error has occurred on its All clock and data inputs are compatible with the JEDEC open-drain PTYERR pin (active LOW). standard for SSTL 18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A Features operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK 28-bit 1:2 registered buffer with parity check functionality going low. Supports SSTL 18 JEDEC specification on data inputs The device supports low-power standby operation. When and outputs the reset input (RESET) is low, the differential input Supports LVCMOS switching levels on CSGateEN and receivers are disabled, and undriven (floating) data, clock RESET inputs and reference voltage (VREF) inputs are allowed. In Low voltage operation: VDD = 1.7V to 1.9V addition, when RESET is low all registers are reset, and all Available in 160-ball LFBGA package outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low Applications state during power up. DDR2 Memory Modules In the DDR2 RDIMM application, RESET is specified to be Provides complete DDR DIMM solution with completely asynchronous with respect to CLK and CLK. ICS98ULPA877A or IDTCSPUA877A Therefore, no timing relationship can be guaranteed Ideal for DDR2 400, 533, 667, and 800 between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the IDT74SSTUBF32865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 1 IDT74SSTUBF32865A 7092/11IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATUREGRADE Block Diagram (CS ACTIVE) VREF D Q PARIN PARITY GENERATOR PTYERR AND R 22 CHECKER Q0A D Q D0 Q0B R Q21A D Q D21 Q21B R QCS0A DCS0 D Q R QCS0B CSGateEN QCS1A DCS1 D Q QCS1B R QCKE0A, QCKE1A DCKE0, 2 2 DCKE1 D Q QCKE0B, R QCKE1B QODT0A, QODT1A DODT0, 2 2 DODT1 D Q QODT0B, R QODT1B RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 2 IDT74SSTUBF32865A 7092/11