74LVC821APW NXP

74LVC821A 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 4 23 November 2012 Product data sheet 1. General description The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an output enable input (pin OE) are common to all flip-flops. The ten flip-flops store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE inputs does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs and outputs; for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Flow-through pinout architecture 10-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C.74LVC821A NXP Semiconductors 10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC821AD 40 C to +125 C SO24 plastic small outline package; 24 leads; SOT137-1 body width 7.5 mm 74LVC821ADB 40 C to +125 C SSOP24 plastic shrink small outline package; 24 leads; SOT340-1 body width 5.3 mm 74LVC821APW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1 body width 4.4 mm 74LVC821ABQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm 4. Functional diagram 13 C1 1 EN 13 CP 2 23 1D 2 23 D0 Q0 3 22 3 22 D1 Q1 4 21 4 21 D2 Q2 5 20 D3 Q3 5 20 6 19 D4 Q4 6 19 7 18 D5 Q5 7 18 8 17 D6 Q6 9 16 8 17 D7 Q7 10 15 9 16 D8 Q8 11 14 D9 Q9 10 15 OE 11 14 1 001aaa677 001aaa678 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC821A All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 23 November 2012 2 of 20