74LVC823A-Q100 9-bit D-type flip-flop with 5 V tolerant inputs/outputs positive edge-trigger 3-state Rev. 3 18 June 2020 Product data sheet 1. General description The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Flow-through pinout architecture 9-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC823ABQ-Q100 -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal SOT815-1 enhanced very thin quad flat package no leads 24 terminals body 3.5 x 5.5 x 0.85 mmNexperia 74LVC823A-Q100 9-bit D-type flip-flop with 5 V tolerant inputs/outputs positive edge-trigger 3-state 4. Functional diagram 2 D0 Q0 23 3 D1 Q1 22 1 EN 4 D2 Q2 21 11 R 5 D3 Q3 20 14 G1 FF0 13 6 D4 Q4 19 11 1 3-STATE 1C2 to OUTPUTS FF8 7 D5 Q5 18 MR OE 2 23 D0 Q0 2 23 2D 8 D6 Q6 17 3 22 D1 Q1 3 22 4 21 9 D7 Q7 16 D2 Q2 4 21 5 20 10 D8 Q8 15 D3 Q3 6 19 5 20 D4 Q4 7 18 D5 Q5 6 19 13 CP 8 17 D6 Q6 7 18 9 16 11 MR D7 Q7 8 17 10 15 14 CE D8 Q8 9 16 CP CE 1 OE 10 15 13 14 001aaa849 001aaa847 001aaa848 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74LVC823A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 18 June 2020 2 / 16