74LVC1G386GW,125 Nexperia

74LVC1G386 3-input EXCLUSIVE-OR gate Rev. 4 9 May 2017 Product data sheet 1 General description The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices in a mixed 3.3 and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range from 1.65 to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V = 3.0 V) CC Latch-up performance exceeds 250 mA CMOS low power consumption Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. SOT363 and SOT457 package Specified from -40 to +85 C and -40 to +125 C.Nexperia 74LVC1G386 3-input EXCLUSIVE-OR gate 3 Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC1G386GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC1G386GV -40 C to +125 C SC-74A plastic surface-mounted package (TSOP6) 6 leads SOT457 4 Marking Table 2. Marking 1 Type number Marking code 74LVC1G386GW YH 74LVC1G386GV YH 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram A 1 B Y 1 = 1 3 4 3 4 C 6 6 mnb143 mnb145 Figure 1. Logic symbol Figure 2. IEC logic symbol A B Y C mnb144 Figure 3. Logic diagram 74LVC1G386 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 4 9 May 2017 2 / 14