74LVC1G38GW-Q100H Nexperia

74LVC1G38-Q100 2-input NAND gate open drain Rev. 4 12 January 2022 Product data sheet 1. General description The 74LVC1G38-Q100 is a single 2-input NAND gate with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Open drain outputs Direct interface with TTL levels Inputs accept voltages up to 5 V Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G38GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 74LVC1G38GV-Q100 -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753Nexperia 74LVC1G38-Q100 2-input NAND gate open drain 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G38GW-Q100 YB 74LVC1G38GV-Q100 YB 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y A 1 A 1 & Y 4 4 2 B 2 B GND 001aab717 001aab716 001aab715 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G38 A 1 5 V CC B 2 3 4 GND Y 001aab718 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 6.2. Pin description Table 3. Pin description Symbol Pin Description A 1 data input B 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74LVC1G38 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 4 12 January 2022 2 / 12