74LVC1G53DP-Q100H Nexperia

74LVC1G53-Q100 2-channel analog multiplexer/demultiplexer Rev. 4 20 July 2021 Product data sheet 1. General description The 74LVC1G53-Q100 is a single-pole double-throw analog switch with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switch is turned off. Control inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at control inputs makes the circuit tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at V = 2.7 V CC 6.5 (typical) at V = 3.3 V CC 6 (typical) at V = 5 V CC Switch current capability of 32 mA High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD 78 Class I ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G53DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC1G53DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mmNexperia 74LVC1G53-Q100 2-channel analog multiplexer/demultiplexer 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC1G53DC-Q100 V53 74LVC1G53DP-Q100 V53 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y1 S Y0 Z E 001aah795 Fig. 1. Logic symbol Y0 S Z Y1 E 001aad387 Fig. 2. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G53 Z 1 8 V CC E 2 7 Y0 GND 3 6 Y1 GND 4 5 S 001aad388 Fig. 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC1G53 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 20 July 2021 2 / 18