74LVC1GU04GM,115 Nexperia

74LVC1GU04 Unbuffered inverter Rev. 15 12 January 2022 Product data sheet 1. General description The 74LVC1GU04 is a single unbuffered inverter. Inputs can be driven from either 3.3 V or 5.5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.65 V to 5.5 V High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low power dissipation Latch-up performance exceeds 250 mA Complies with JEDEC standard no. 8-1A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1GU04GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 74LVC1GU04GV -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74LVC1GU04GM -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mm 74LVC1GU04GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVC1GU04GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74LVC1GU04GX -40 C to +125 C X2SON5 plastic thermal enhanced extremely thin SOT1226-3 small outline package no leads 5 terminals body 0.8 0.8 0.32 mmNexperia 74LVC1GU04 Unbuffered inverter 4. Marking Table 2. Marking codes Type number Marking 1 74LVC1GU04GW VD 74LVC1GU04GV VU4 74LVC1GU04GM VD 74LVC1GU04GN VD 74LVC1GU04GS VD 74LVC1GU04GX VD 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V V CC CC 100 Y A A Y 1 mna108 mna109 mna636 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1GU04 74LVC1GU04 n.c. 1 6 V CC n.c. 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aab667 001aab666 Transparent top view Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) Fig. 5. Pin configuration SOT886 (XSON6) 74LVC1GU04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 15 12 January 2022 2 / 18