74LVC257AD,112 Nexperia

74LVC257A Quad 2-input multiplexer with 5 V tolerant inputs/outputs 3-state Rev. 8 31 August 2021 Product data sheet 1. General description The 74LVC257A is a quad 2-input multiplexer 3-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at 85 C I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC257AD -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC257APW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC257ABQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mmNexperia 74LVC257A Quad 2-input multiplexer with 5 V tolerant inputs/outputs 3-state 4. Functional diagram 1 G1 15 1I0 2 EN 3 1I1 2 MUX 1 1Y 2I0 5 4 4 3 1 2Y 6 2I1 7 5 7 11 3I0 3Y 9 6 10 12 3I1 4Y 11 9 14 4I0 10 13 4I1 14 12 S OE 13 mna865 1 15 mna866 Fig. 1. Logic diagram Fig. 2. IEC logic symbol 1I1 1Y 1I0 2I1 2Y 2I0 1I0 2 1Y 4 1I1 3 3I1 3Y 2I0 5 2Y 7 3-STATE 2I1 6 3I0 MULTI- SELECTOR 3I0 11 PLEXER 3Y 9 OUTPUTS 3I1 10 4I1 4I0 4Y 14 4Y 12 4I1 13 4I0 S 1 OE 15 OE S mna867 mna868 Fig. 3. Functional diagram Fig. 4. Logic diagram 74LVC257A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 31 August 2021 2 / 14