74LVC273BQ Nexperia

74LVC273 Octal D-type flip-flop with reset positive-edge trigger Rev. 6 31 December 2012 Product data sheet 1. General description The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at +85 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C74LVC273 NXP Semiconductors Octal D-type flip-flop with reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC273D 40 Cto +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC273DB 40 Cto +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LVC273PW 40 Cto +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC273BQ 40 Cto +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 CP C1 1 R MR 11 3 2 CP 1D D0 Q0 3 2 D0 Q0 4 5 4 5 D1 Q1 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 D4 Q4 13 12 D4 Q4 14 15 D5 Q5 14 15 D5 Q5 17 16 D6 Q6 17 16 18 19 D6 Q6 D7 Q7 MR 18 19 D7 Q7 1 mna763 mna764 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC273 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 31 December 2012 2 of 17