74LVC2GU04GM,115 Nexperia

74LVC2GU04 Dual inverter Rev. 8 3 July 2012 Product data sheet 1. General description The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Input accepts voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2GU04GW 40 Cto+125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC2GU04GV 40 Cto+125 C TSOP6 plastic surface-mounted package (TSOP6) SOT457 6 leads 74LVC2GU04GM 40 Cto+125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mm 74LVC2GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package SOT891 no leads 6 terminals body 1 1 0.5 mm 74LVC2GU04GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVC2GU04GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm74LVC2GU04 NXP Semiconductors Dual inverter 4. Marking Table 2. Marking codes 1 Type number Marking 74LVC2GU04GW YD 74LVC2GU04GV VU4 74LVC2GU04GM YD 74LVC2GU04GF YD 74LVC2GU04GN YD 74LVC2GU04GS YD 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V V CC CC 1 1A 1Y 6 1 1 6 100 Y A 1 3 2A 2Y 4 3 4 mnb106 mnb107 mna636 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2GU04 74LVC2GU04 1A 1 6 1Y 74LVC2GU04 1A 1 6 1Y 1A 1 6 1Y GND 2 5 V CC GND 2 5 V CC GND 2 5 V CC 2A 3 4 2Y 2A 3 4 2Y 2A 3 4 2Y 001aab681 001aag421 Transparent top view Transparent top view 001aab680 Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, and SOT457 SOT1115 and SOT1202 74LVC2GU04 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 8 3 July 2012 2 of 19