74LVC595AD,118 Nexperia

74LVC595A 8-bit serial-in/serial-out or parallel-out shift register 3-state Rev. 3 19 November 2021 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry disables the output, preventing the OFF OFF potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power dissipation Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC595AD -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC595APW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC595ABQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 5. Functional diagram 11 12 SHCP STCP 14 DS 9 Q7S 11 SHCP 15 8-STAGE SHIFT REGISTER Q0 10 MR 1 Q1 Q7S 9 2 Q2 14 3 12 STCP DS Q3 8-BIT STORAGE REGISTER 4 Q4 5 Q5 6 Q6 13 OE 3-STATE OUTPUTS 7 Q7 MR OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 10 13 mna552 15 1 2 3 4 5 6 7 mna554 Fig. 1. Logic symbol Fig. 2. Functional diagram 74LVC595A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 19 November 2021 2 / 18