74LVC74ABQ,115 Nexperia

74LVC74A Dual D-type flip-flop with set and reset positive-edge trigger Rev. 7 20 November 2012 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features and benefits 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC74ADB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LVC74APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC74ABQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram 1SD 4 SD 1Q 1D 2 D Q 5 1CP 3 CP FF 1Q Q 6 RD 4 410 S 5 1RD 3 1 1SD 2SD C1 2 2SD 1D 6 10 SD 1 1Q 5 2 1D R D Q 12 2D 2Q 9 SD 2Q 2D 3 1CP 12 9 D Q CP 10 11 2CP FF S 9 2CP 1Q 6 11 CP 11 Q C1 8 FF 2Q 2Q 12 RD Q 8 1D 8 13 RD 1RD 2RD R 2RD 113 mna420 mna418 mna419 13 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram 74LVC74A All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 20 November 2012 2 of 19