HEF4021BP Nexperia

HEF4021B 8-bit static shift register Rev. 9 30 August 2013 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Tolerant of slower rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Version Name Description HEF4021BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4021BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 HEF4021BTT TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1HEF4021B NXP Semiconductors 8-bit static shift register 4. Functional diagram 7 6 5 4 13 14 15 1 D0 D1 D2 D3 D4 D5 D6 D7 9PL SD/CD 11 DS D SHIFT REGISTER 10 CP 8-BITS CP Q5 Q6 Q7 2 12 3 001aae608 Fig 1. Functional diagram D0 D5 D6 D7 SD SD SD SD DS D O D O D O D O CP CP CP CP FF 1 FF 6 FF 7 FF 8 CD CD CD CD PL CP Q5 Q6 Q7 001aae610 Fig 2. Logic diagram HEF4021B All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 9 30 August 2013 2 of 16