HEF4053BT-Q100J Nexperia

HEF4053B-Q100 Triple single-pole double-throw analog switch Rev. 3 21 December 2021 Product data sheet 1. General description The HEF4053B-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (Y0 and Y1) and a common input/output (Z). A digital enable input (E) is common to all switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4053BT-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm HEF4053BTT-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mmNexperia HEF4053B-Q100 Triple single-pole double-throw analog switch 5. Functional diagram E V DD 6 16 13 1Y1 LOGIC S1 11 12 1Y0 LEVEL DECODER CONVERSION 14 1Z 1 2Y1 LOGIC S2 10 2 2Y0 LEVEL CONVERSION 11 S1 1Y0 12 15 2Z 10 S2 1Y1 13 9 S3 1Z 14 3 3Y1 2Y0 2 2Y1 1 LOGIC S3 9 5 3Y0 LEVEL 2Z 15 CONVERSION 3Y0 5 4 3Z 3Y1 3 6 E 3Z 4 8 7 V V 001aae124 SS EE 001aae125 Fig. 1. Logic symbol Fig. 2. Functional diagram nZ nY1 LEVEL Sn CONVERTER nY0 LEVEL E CONVERTER to other multiplexers/demultiplexers 001aae645 Fig. 3. Logic diagram (one multiplexer/demultiplexer) HEF4053B Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 21 December 2021 2 / 16