PSMN2R0-25MLD N-channel 25 V, 2.1 m logic level MOSFET in LFPAK33 using NextPowerS3 Technology 8 April 2016 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK33 package. NextPowerS3 portfolio utilising NXPs unique SchottkyPlus technology delivers high efficiency, low spiking performance usually associated with MOSFETS with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits Ultra low Q , Q and Q for high system efficiency, especially at higher switching G GD OSS frequencies Superfast switching with soft-recovery s-factor > 1 Low spiking and ringing for low EMI designs Unique SchottkyPlus technology Schottky-like performance with < 1 A leakage at 25 C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Mini Power SO8 package no glue, no wire bonds, qualified to 175 C Exposed leads for optimal visual solder inspection 3. Applications On-board DC:DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage 25 C T 175 C - - 25 V DS j I drain current V = 10 V T = 25 C Fig. 2 - - 70 A D GS mb P total power dissipation T = 25 C Fig. 1 - - 74 W tot mb Scan or click this QR code to view the latest information for this product LFPAK33NXP Semiconductors PSMN2R0-25MLD N-channel 25 V, 2.1 m logic level MOSFET in LFPAK33 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit T junction temperature -55 - 175 C j Static characteristics R drain-source on-state V = 4.5 V I = 25 A T = 25 C - 2.5 3.06 m DSon GS D j resistance Fig. 10 V = 10 V I = 25 A T = 25 C - 1.86 2.27 m GS D j Fig. 10 Dynamic characteristics Q total gate charge I = 25 A V = 12 V V = 10 V - 34.4 - nC G(tot) D DS GS Fig. 12 Fig. 13 I = 25 A V = 12 V V = 4.5 V - 15.9 - nC D DS GS Fig. 12 Fig. 13 I = 0 A V = 0 V V = 10 V - 18.9 - nC D DS GS Q gate-drain charge I = 25 A V = 12 V V = 4.5 V - 3.8 - nC GD D DS GS Fig. 12 Fig. 13 Source-drain diode S softness factor I = 25 A dI /dt = -100 A/s V = 0 V - 0.9 - S S GS V = 12 V Fig. 16 DS 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source D 2 S source G 3 S source mbb076 S 4 G gate mb D mounting base connected to 1 2 3 4 drain LFPAK33 (SOT1210) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN2R0-25MLD LFPAK33 Plastic single ended surface mounted package SOT1210 (LFPAK33) 8 leads PSMN2R0-25MLD All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved Product data sheet 8 April 2016 2 / 13