PSMN4R2-40VSH Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 16 August 2021 Product data sheet 1. General description D1 Dual, standard level N-channel MOSFET in an LFPAK56D package (half- bridge configuration), using NextpowerS3 technology. An internal connection is made between the source (S1) of the high-side G1 FET to the drain (D2) of the low-side FET, making the device ideal to use S1, D2 as a half-bridge switch in high-performance PWM and space constrained G2 motor drive applications S2 aaa-028081 2. Features and benefits LFPAK56D package with half-bridge configuration enables: Reduced PCB layout complexity Module shrinkage through reduced component count Improved system level R due to optimized package design th(j-amb) Lower parasitic inductance to support higher efficiency Footprint compatibility with LFPAK56D Dual package NextpowerS3 technology Low power losses, high power density Superior avalanche performance Repetitive avalanche rated LFPAK copper clip packaging provides high robustness and reliability Gull wing leads support high manufacturability and Automated Optical Inspection (AOI) 3. Applications Handheld power tools, portable appliance and space constrained applications Brushless or brushed DC motor drive DC-to-DC systems LED lighting 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Limiting values FET1 and FET2 V drain-source voltage 25 C T 175 C - - 40 V DS j I drain current V = 10 V T = 25 C Fig. 2 1 - - 98 A D GS mb P total power dissipation T = 25 C Fig. 1 - - 85 W tot mb T junction temperature -55 - 175 C jNexperia PSMN4R2-40VSH Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Typ Max Unit Static characteristics FET1 and FET2 R drain-source on-state V = 10 V I = 20 A T = 25 C Fig. 8 - 3.5 4.2 m DSon GS D j resistance Dynamic characteristics FET1 and FET2 Q gate-drain charge I = 20 A V = 32 V V = 10 V 1.4 4.7 9.4 nC GD D DS GS Fig. 10 Fig. 11 Q total gate charge 17 26 37 nC G(tot) 1 98A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S2 source2 8 7 6 5 D1 2 G2 gate2 3 S1 source1 G1 4 G1 gate1 S1, D2 5 D1 drain1 6 D1 drain1 G2 7 S1, D2 source1, drain2 1 2 3 4 S2 aaa-028081 8 S1, D2 source1, drain2 LFPAK56D Dual LFPAK (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN4R2-40VSH LFPAK56D plastic, single ended surface mounted package SOT1205 Dual LFPAK (LFPAK56D) 8 leads 7. Marking Table 4. Marking codes Type number Marking code 4H2S40V PSMN4R2-40VSH 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Limiting values FET1 and FET2 V drain-source voltage 25 C T 175 C - 40 V DS j V peak drain-source t = 20 ns f = 500 kHz E = 200 nJ - 45 V DSM p DS(AL) voltage pulsed PSMN4R2-40VSH All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet 16 August 2021 2 / 12