74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable 3-state Rev. 6 20 October 2020 Product data sheet 1. General description The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Bus hold on data inputs Power-up 3-state I circuitry provides partial Power-down mode operation OFF Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Live insertion and extraction permitted Power-up reset No bus current loading when output is tied to 5 V bus Output capability: +64 mA to -32 mA Latch-up performance exceeds 500 mA per JESD 78 Class II Level B ESD protection: MIL STD 883, method 3015: exceeds 2000 V MM: exceeds 200 V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVT16823DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mmNexperia 74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable 3-state 4. Functional diagram 2 1OE EN1 1 1MR R2 55 1CE G3 56 1CP 3C4 27 2OE EN5 28 2MR R6 30 2CE G7 29 2CP 7C8 54 3 1D0 4D 1,2 1Q0 52 5 1D1 1Q1 51 6 1D2 1Q2 49 8 1D3 1Q3 48 9 1D4 1Q4 47 10 1D5 1Q5 45 12 1D6 1Q6 44 13 1D7 1Q7 43 14 1D8 1Q8 V CC 42 15 2D0 8D 5,6 2Q0 41 16 2D1 2Q1 40 17 2D2 2Q2 38 19 2D3 2Q3 37 20 data input to internal circuit 2D4 2Q4 36 21 2D5 2Q5 34 23 2D6 2Q6 33 24 2D7 2Q7 31 26 2D8 2Q8 001aad242 001aad245 Fig. 1. IEC logic symbol Fig. 2. Bushold circuit (one data input) 74ALVT16823 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 20 October 2020 2 / 16