74AUP1GU04GM,132 NXP

74AUP1GU04 Low-power unbuffered inverter Rev. 5 29 June 2012 Product data sheet 1. General description The 74AUP1GU04 provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1GU04GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1 body width 1.25 mm 74AUP1GU04GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm 74AUP1GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm 74AUP1GU04GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 1.0 0.35 mm 74AUP1GU04GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 1.0 0.35 mm 74AUP1GU04GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226 small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm74AUP1GU04 Nexperia Low-power unbuffered inverter 4. Marking Table 2. Marking [1] Type number Marking code 74AUP1GU04GW pD 74AUP1GU04GM pD 74AUP1GU04GF pD 74AUP1GU04GN pD 74AUP1GU04GS pD 74AUP1GU04GX pD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V CC 540 50 AY 2AY 4 1 2 4 mna108 mna109 001aad073 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1GU04 74AUP1GU04 n.c. 1 6 V CC n.c. 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aaf168 Transparent top view 001aaf167 Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886 74AUP1GU04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 29 June 2012 2 of 21