74AUP2G98GFX NXP

74AUP2G98 Low-power dual PCB configurable multiple function gate Rev. 3 11 December 2020 Product data sheet 1. General description The 74AUP2G98 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer using the 3-bit input. All inputs can be connected directly to V or GND. CC This device ensures very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP2G98 Low-power dual PCB configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G98DP -40 C to +125 C TSSOP10 plastic thin shrink small outline package 10 leads SOT552-1 body width 3 mm 74AUP2G98GU -40 C to +125 C XQFN10 plastic, extremely thin quad flat package no leads SOT1160-1 10 terminals body 1.40 1.80 0.50 mm 4. Marking Table 2. Marking Type number Marking code 1 74AUP2G98DP a9 74AUP2G98GU a9 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram nA nY nB nC aaa-015408 Fig. 1. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74AUP2G98 terminal 1 index area 1B 1 7 2C 74AUP2G98 1C 2 6 2B 1 10 V 1A CC 1B 2 9 1Y 3 8 2C 1C 4 7 2Y 2B GND 5 6 2A Transparent top view aaa-015409 aaa-015411 Fig. 2. Pin configuration SOT552-1 (TSSOP10) Fig. 3. Pin configuration SOT1160-1 (XQFN10) 74AUP2G98 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 11 December 2020 2 / 17 2Y 3 10 1A GND 4 9 V CC 2A 5 8 1Y