74HC109N,652 NXP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT109 Dual JK flip-flop with set and reset positive-edge trigger 1997 Nov 25 Product specication Supersedes data of December 1990 File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual JK ip-op with set and reset 74HC/HCT109 positive-edge trigger FEATURES (S ) and reset (R ) inputs also complementary Q and Q D D outputs. J, K inputs for easy D-type flip-flop The set and reset are asynchronous active LOW inputs Toggle flip-flop or do nothing mode and operate independently of the clock input. Output capability: standard The J and K inputs control the state changes of the I category: flip-flops CC flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to GENERAL DESCRIPTION the LOW-to-HIGH clock transition for predictable The 74HC/HCT109 are high-speed Si-gate CMOS devices operation. and are pin compatible with low power Schottky TTL The JK design allows operation as a D-type flip-flop by (LSTTL). They are specified in compliance with JEDEC tying the J and K inputs together. standard no. 7A. Schmitt-trigger action in the clock input makes the circuit The 74HC/HCT109 are dual positive-edge triggered, JK highly tolerant to slower clock rise and fall times. flip-flops with individual J, K inputs, clock (CP) inputs, set QUICK REFERENCE DATA GND = 0 V T = 25 C t = t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay PHL PLH nCP to nQ, nQ1517ns C = 15 pF L nS to nQ, nQ1214ns D V = 5 V CC nR to nQ, nQ1215ns D f maximum clock frequency 75 61 MHz max C input capacitance 3.5 3.5 pF I C power dissipation 20 22 pF PD notes 1 and 2 capacitance per ip-op Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V. I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. 1997 Nov 25 2