74HC10D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10 Triple 3-input NAND gate December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Triple 3-input NAND gate 74HC/HCT10 FEATURES Output capability: standard I category: SSI CC GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay nA, nB, nC to nY C = 15 pF V =5V 9 11 ns PHL PLH L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per gate notes 1 and 2 12 14 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC O f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC 2 (C V f ) = sum of outputs L CC o 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V. I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2