INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT194 4-bit bidirectional universal shift register December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 4-bit bidirectional universal shift register 74HC/HCT194 FEATURES and shifted from left to right (Q Q Q , etc.) or, right 0 1 2 to left (Q Q Q , etc.) or parallel data can be 3 2 1 Shift-left and shift-right capability entered, loading all 4 bits of the register simultaneously. Synchronous parallel and serial data transfer When both S and S are LOW, existing data is retained in 0 1 a hold (do nothing) mode. The first and last stages Easily expanded for both serial and parallel operation provide D-type serial data inputs (D , D ) to allow SR SL Asynchronous master reset multistage shift right or shift left data transfers without Hold (do nothing) mode interfering with parallel load operation. Output capability: standard Mode select and data inputs are edge-triggered, I category: MSI CC responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one GENERAL DESCRIPTION set-up time prior to the positive transition of the clock The 74HC/HCT194 are high-speed Si-gate CMOS devices pulse. and are pin compatible with low power Schottky TTL The four parallel data inputs (D to D ) are D-type inputs. 0 3 (LSTTL). They are specified in compliance with JEDEC Data appearing on the D to D inputs, when S and S are 0 3 0 1 standard no. 7A. HIGH, is transferred to the Q to Q outputs respectively, 0 3 The functional characteristics of the 74HC/HCT194 4-bit following the next LOW-to-HIGH transition of the clock. bidirectional universal shift registers are indicated in the When LOW, the asynchronous master reset (MR) logic diagram and function table. The registers are fully overrides all other input conditions and forces the Q synchronous. outputs LOW. The 194 design has special features which increase the The 194 is similar in operation to the 195 universal shift range of application. The synchronous operation of the register, with added features of shift-left without external device is determined by the mode select inputs (S , S ). 0 1 connections and hold (do nothing) modes of operation. As shown in the mode select table, data can be entered QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5 V PHL PLH L CC CP to Q 14 15 ns n t MR to Q 11 15 ns PHL n f maximum clock frequency 102 77 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 40 40 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 =(C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V for HCT the condition is V = GND to V - 1.5 V I CC I CC December 1990 2