HCF40103B 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS SYNCHRONOUS OR ASYNCHRONOUS PRESET MEDIUM -SPEED OPERATION : f =3.6MHz (Typ.) at V = 10V CL DD CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V DIP SOP 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT V = 18V T = 25C I DD A 100% TESTED FOR QUIESCENT CURRENT ORDER CODES MEETS ALL REQUIREMENTS OF JEDEC PACKAGE TUBE T & R JESD13BSTANDARD SPECIFICATIONS DIP HCF40103BEY FOR DESCRIPTION OF B SERIES CMOS SOP HCF40103BM1 HCF40103M013TR DEVICE CE) input is high. The CARRY-OUT/ZERO DESCRIPTION DETECT (CO/ZD) output goes low when the HCF40103B is a monolithic integrated circuit count reaches zero if the CI/CE input is low, and fabricated in Metal Oxide Semiconductor remains low for one full clock period. When the technology available in DIP and SOP packages. SYNCHRONOUS PRESET ENABLE (SPE) input is low, data at the JAM input is clocked into the HCF40103B consists of an 8-stage synchronous down counter with a single output that is active counter on the next positive clock transition when the internal count is zero. This device regardless of the state of the CI/CE input. When contains a single 8-bit binary counter. It has the ASYNCHRONOUS PRESET ENABLE (APE) input is low, data at the JAM inputs is control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and asynchronously forced into the counter regardless for presetting the counter either synchronously or of the state of the SPE, CI/CE, or CLOCK inputs. asynchronously. All control inputs and the JAM inputs J0-J7 represent a single 8 bit binary word. When the CLEAR (CLR) input is low, the CARRY-OUT/ZERO DETECT output are active-low logics. In normal operation, the counter counter is asynchronously cleared to its maximum is decremented by one count on each positive count (255 ) regardless of the state of any other 10 transition of the CLOCK. Counting is inhibited input. The precedent relationship between control input is indicated in the truth table. If all control when the CARRY-IN/COUNTER ENABLE (CI/ PIN CONNECTION September 2002 1/14 Obsolete Product(s) - Obsolete Product(s)HCF40103B inputs are high at the time of zero count, the HCF40103B may be cascaded using the CI/CE counters will jump to the maximum count, giving a input and the CO/ZD output, in either a counting sequence of 256 clock pulses long. synchronous or ripple mode. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Clock Input (LOW to 1 CLOCK HIGH edge triggered) Asynchronous Master 2 CLEAR Reset Input (Active Low) 3 CI/CE Terminal Enable Input 4, 5, 6, 7, 10, J0 to J7 Jam Inputs 11, 12, 13 Asynchronous Preset 9APE Enable Inputs(Active Low) Terminal Count Output 14 CO/ZD (Active Low) Synchronous Preset 15 SPE Enable Input (Active Low) V 8 Negative Supply Voltage SS V 16 Positive Supply Voltage DD FUNCTIONAL DIAGRAM TRUTH TABLES CONTROL INPUTS PRESET MODE ACTION CLR APE SPE CI/CE HH HH Inhibit Counter H H H L Synchronous Count Down H H L X Preset on Next Positive Clock Transition HL X X Preset Asynchronously Asynchronous L X X X Clear to Maximum Count X : Dont Care Clock connected to Clock input Synchronous Operation : changes occur on negative to positive clock transitions. 2/14 Obsolete Product(s) - Obsolete Product(s)