74HC373N,652 NXP

74HC373; 74HCT373 Octal D-type transparent latch; 3-state Rev. 5 13 December 2011 Product data sheet 1. General description The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high- impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HC373; 74HCT373 is functionally identical to: 74HC563; 74HCT563: but inverted outputs and different pin arrangement 74HC573; 74HCT573: but different pin arrangement 2. Features and benefits 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573 ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+85 C and from 40 Cto+125 C74HC373; 74HCT373 NXP Semiconductors Octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC373N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74HCT373N 74HC373D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HCT373D 74HC373DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74HCT373DB 74HC373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74HCT373PW 74HC373BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; 74HCT373BQ body 2.5 4.5 0.85 mm 4. Functional diagram D0 Q0 3 2 D1 Q1 4 5 D2 Q2 7 6 D3 Q3 8 9 LATCH 3-STATE D4 Q4 1 TO 8 OUTPUTS 13 12 D5 Q5 14 15 D6 Q6 17 16 D7 Q7 18 19 LE 11 OE 1 001aae050 Fig 1. Functional diagram 74HC_HCT373 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 13 December 2011 2 of 26