INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT563
Octal D-type transparent latch;
3-state; inverting
December 1990
Product specication
File under Integrated Circuits, IC06Philips Semiconductors Product specication
Octal D-type transparent latch; 3-state;
74HC/HCT563
inverting
FEATURES TTL (LSTTL). They are specified in common to all latches.
compliance with JEDEC standard no. When LE is HIGH, data at the D
n
3-state inverting outputs for bus
7A. inputs enter the latches. In this
oriented applications
condition the latches are transparent,
The 74HC/HCT563 are octal D-type
Inputs and outputs on opposite
i.e. a latch output will change state
transparent latches featuring
sides of package allowing easy
each time its corresponding D-input
separate D-type inputs for each latch
interface with microprocessor
changes.
and inverting 3-state outputs for bus
Common 3-state output enable
oriented applications. When LE is LOW the latches store the
input
A latch enable (LE) input and an information that was present at the
Output capability: bus driver
output enable (OE) input are common D-inputs a set-up time preceding the
to all latches. HIGH-to-LOW transition of LE.
I category: MSI
CC
When OE is LOW, the contents of the
The 563 is functionally identical to
8 latches are available at the outputs.
the 573, but has inverted outputs.
GENERAL DESCRIPTION
When OE is HIGH, the outputs go to
The 563 consists of eight D-type the high impedance OFF-state.
The 74HC/HCT563 are high-speed
transparent latches with 3-state Operation of the OE input does not
Si-gate CMOS devices and are pin
inverting outputs. The LE and OE are affect the state of the latches.
compatible with low power Schottky
QUICK REFERENCE DATA
GND = 0 V; T =25 C; t =t = 6 ns
amb r f
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
t t propagation delay D , LE to Q C = 15 pF; V =5 V 14 16 ns
PHL/ PLH n n L CC
C input capacitance 3.5 3.5 pF
I
C power dissipation capacitance per latch notes 1 and 2 19 19 pF
PD
Notes
1. C is used to determine the dynamic power dissipation (P in W):
PD D
2 2
P =C V f + (C V f ) where:
D PD CC i L CC o
f = input frequency in MHz
i
f = output frequency in MHz
o
2
(C V f ) = sum of outputs
L CC o
C = output load capacitance in pF
L
V = supply voltage in V
CC
2. For HC the condition is V = GND to V
I CC
for HCT the condition is V = GND to V - 1.5 V
I CC
ORDERING INFORMATION
See 74HC/HCT/HCU/HCMOS Logic Package Information.
December 1990 2