74HC40103N NXP

74HC40103 8-bit synchronous binary down counter Rev. 03 12 November 2004 Product data sheet 1. General description The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the 40103 of the 4000B series. The 74HC40103 is specied in compliance with JEDEC standard no. 7A. The 74HC40103 consists of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The 74HC40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode.74HC40103 Philips Semiconductors 8-bit synchronous binary down counter 2. Features Cascadable Synchronous or asynchronous preset Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Multiple package options Specied from - 40 Cto+80 C and from - 40 C to +125 C. 3. Applications Divide-by-n counters Programmable timers Interrupt timers Cycle/program counters. 4. Quick reference data Table 1: Quick reference data GND = 0 V; T =25 C; t =t = 6 ns. amb r f Symbol Parameter Conditions Min Typ Max Unit t , t propagation delay CP to TC C = 15 pF; -30 - ns PHL PLH L V = 5 V CC f maximum clock frequency C = 15 pF; - 32 - MHz max L V = 5 V CC C input capacitance - 3.5 - pF I [1] C power dissipation V = GND to V -24 - pF PD I CC capacitance [1] C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz; i f = output frequency in MHz; o C = output load capacitance in pF; L V = supply voltage in V; CC N = number of inputs switching; 2 (C V f ) = sum of outputs. L CC o 9397 750 13812 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 12 November 2004 2 of 25