74HC74N NXP

74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 5 3 December 2015 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC74: CMOS level For 74HCT74: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-1 3.9 mm 74HCT74D 74HC74DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body SOT337-1 width 5.3 mm 74HCT74DB74HC74; 74HCT74 Nexperia Dual D-type flip-flop with set and reset; positive edge-trigger Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74HC74PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74HCT74PW 74HC74BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; 74HCT74BQ body 2.5 3 0.85 mm 4. Functional diagram 6'  6' ' 4  ' 4  &3  )) 4 4    6  5'   ' 6'  6'  6'  4   5 ' 4 4  6' ' 4  3  ' 4 3 )) 6  &3 4  4  )) 4 4 4   ' 5' 5 5'  DPQ DP Q DP Q Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram 4 & & & & & & ' 4 & & 6' PQ & & Fig 4. Logic diagram for one flip-flop 74HC_HCT74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 3 December 2015 2 of 20 &3 D 5'  5 5'  ' 5'  &  &3  &   &3  & '  '  ' & 6 5' &3