74HCT107N NXP

74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 5 30 November 2015 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: The 74HC107: CMOS levels The 74HCT107: TTL levels ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC107D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-1 3.9 mm 74HCT107D 74HC107DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body SOT337-1 width 5.3 mm 74HC107PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body SOT402-1 width 4.4 mm74HC107; 74HCT107 Nexperia Dual JK flip-flop with reset; negative-edge trigger 4. Functional diagram    &  -   - 4  -    5 ))  &3 &3  &3   . 4  . 4  .  4  & 5   5 5    DDD DDD Fig 1. Logic symbol Fig 2. IEC logic symbol & & & & . 4 - & & & & 5 4 & DED & Fig 3. Logic diagram (one flip-flop) 74HC_HCT107 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 30 November 2015 2 of 18 &3 5 .   - 4 . 4 -