74HCT30DB,118 NXP

74HC30 74HCT30 8-input NAND gate Rev. 9 6 September 2021 Product data sheet 1. General description The 74HC30 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC30: CMOS level For 74HCT30: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC30D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT30D 74HC30PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT30PWNexperia 74HC30 74HCT30 8-input NAND gate 4. Functional diagram 1 A 1 & 2 B 2 3 C 3 4 D 4 Y 8 8 5 E 5 6 F 6 11 G 11 12 H 12 mna488 mna489 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A B C D Y E mna490 F G H Fig. 3. Logic diagram 5. Pinning information 5.1. Pinning 74HC30 74HCT30 A 1 14 V CC B 2 13 n.c. C 3 12 H D 4 11 G E 5 10 n.c. F 6 9 n.c. GND 7 8 Y 001aal790 Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 74HC HCT30 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 6 September 2021 2 / 13