74HCT40105D,112 NXP

74HC40105 74HCT40105 4-bit x 16-word FIFO register Rev. 3 25 September 2013 Product data sheet 1. General description The 74HC40105 74HCT40105 is a first-in/first-out (FIFO)elasti storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The clock pulse transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have buffered outputs. All empty locationsbubbl automatically to the input end, and all valid data ripples through to the output end. As a result, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop (data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Independent asynchronous inputs and outputs Expandable in either direction Reset capability Status indicators on inputs and outputs 3-state outputs Input levels: For 74HC40105: CMOS level For 74HCT40105: TTL level 3-state outputs Complies with JEDEC standard JESD7A ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C74HC40105 74HCT40105 NXP Semiconductors 4-bit x 16-word FIFO register 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74HC40105N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HCT40105N 74HC40105D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT40105D 74HC40105DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT40105DB 74HC40105PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4. Functional diagram 2 ),) (1 >,5 >25 5 & 7& 7& 7& 6, 62 5 DDD DDD Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC HCT40105 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 25 September 2013 2 of 37 05 , 25 = 4 * 4 * 4 &7 4 = 2(