74LV00BQ NXP

74LV00 Quad 2-input NAND gate Rev. 03 20 December 2007 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function. 2. Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV00N - 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74LV00D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV00DB - 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV00PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV00BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm74LV00 NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 9 3A 3Y 8 & 8 10 3B 10 A 12 4A 12 4Y 11 Y 13 4B & 11 13 B mna212 mna246 mna211 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74LV00 terminal 1 index area 2 13 1B 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 2A 4 11 4Y 1Y 3 12 4A 2A 4 00 11 4Y (1) 2B 5 10 3B V CC 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y 001aah092 001aac938 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration DIP14, SO14 and (T)SSOP14 Fig 5. Pin conguration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 1Y 3 data output 2A 4 data input 2B 5 data input 2Y 6 data output 74LV00 3 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 20 December 2007 2 of 14 7 1 GND 1A 3Y 8 14 V CC