74LV00DB,118 NXP

74LV00 Quad 2-input NAND gate Rev. 4 9 December 2015 Product data sheet 1. General description The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC00 and 74HCT00. The 74LV00 provides a quad 2-input NAND function. 2. Features and benefits Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T = 25 C amb ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV00D 40 Cto+125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LV00DB 40 Cto+125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LV00PW 40 Cto+125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LV00BQ 40 Cto+125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm&&  < *1' 74LV00 Nexperia Quad 2-input NAND gate 4. Functional diagram    $    %   $     %  $     % $  $  <  % % DPQ PQ PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning  9 /  WHUPDO LQ 9 QGH[DUHDL    $   9   %   %   <   $ $   <    9 %   %     <   $ '    <  DFD WYR HL U 7 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to V . CC Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LV00 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 4 9 December 2015 2 of 14 $ DQVSDUQWSHZ DDK *1 $ < && % %   < $ $ < && % % D D   <   < < <