74LVC10A
Triple 3-input NAND gate
Rev. 5 17 November 2011 Product data sheet
1. General description
The 74LVC10A provides three 3-input NAND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85 C and 40 Cto+125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC10AD 40 Cto +125 C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
74LVC10ADB 40 Cto +125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1
body width 5.3 mm
74LVC10APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74LVC10ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm74LVC10A
NXP Semiconductors
Triple 3-input NAND gate
4. Functional diagram
1
&
12
2
1 1A
1Y 13
12
2 1B
13 1C
3
3
2A
&
6
4
2Y
4 2B 6
5
5 2C
A
9 3A
9
3Y
8
10 3B
&
Y
10 8 B
11 3C
11
C
mna757 mna759 mna758
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LVC10A
74LVC10A
terminal 1
1A 1 14 V
CC index area
1B 2 13 1C
1B 2 13 1C
2A 3 12 1Y
2A 3 12 1Y
2B 4 11 3C
2B 4 11 3C
2C 5 10 3B
(1)
GND
5 10
2C 3B
6 9
2Y 3A
2Y 6 9 3A
001aad048
GND 7 8 3Y
001aad047 Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A 1, 3, 9 data input
1B, 2B, 3B 2, 4, 10 data input
1C, 2C, 3C 13, 5, 11 data input
74LVC10A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 17 November 2011 2 of 14
GND 7 1 1A
3Y 8 14 V
CC