74LV132D,118 NXP

74LV132 Quad 2-input NAND Schmitt trigger Rev. 7 20 May 2020 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is defined as the input hysteresis T+ T- voltage V . H 2. Features and benefits Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Applications Wave and pulse shapers for highly noisy environments Astable multivibrators Monostable multivibrators 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV132D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV132DB -40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74LV132PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV132BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LV132 Quad 2-input NAND Schmitt trigger 5. Functional diagram 1A 1 1Y 3 1B 2 2A 4 1 2Y 6 & 3 2B 2 5 4 & 3A 6 9 5 3Y 8 3B 9 10 & 8 10 4A 12 A 12 4Y & 11 11 Y 13 4B 13 B mna407 mna408 mna409 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74LV132 terminal 1 index area 74LV132 1B 2 13 4B 1Y 3 12 4A 1A 1 14 V CC 4 11 2A 4Y 2 13 1B 4B (1) 2B 5 10 3B V CC 1Y 3 12 4A 2Y 6 9 3A 2A 4 11 4Y 2B 5 10 3B 001aah099 Transparent top view 2Y 6 9 3A (1) This is not a supply pin. There is no electrical or 7 8 GND 3Y mechanical requirement to solder the pad. In case 001aac203 soldered, the solder land should remain floating or connected to V CC Fig. 4. Pin configuration SOT108-1 (SO14), SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74LV132 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 7 20 May 2020 2 / 15 GND 7 1 1A 3Y 8 14 V CC