74LV132PW NXP

74LV132 Quad 2-input NAND Schmitt trigger Rev. 6 9 December 2015 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is defined as the T+ T input hysteresis voltage V . H 2. Features and benefits Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T = 25 C amb ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Applications Wave and pulse shapers for highly noisy environments Astable multivibrators Monostable multivibrators74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV132D 40 Cto+125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV132DB 40 Cto+125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV132PW 40 Cto+125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV132BQ 40 Cto+125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 5. Functional diagram < % < % < % < < % % D P Q D P Q D PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LV132 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 9 December 2015 2 of 17