74LVC132AD Nexperia

74LVC132A Quad 2-input NAND Schmitt trigger Rev. 3 7 December 2011 Product data sheet 1. General description The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is defined as the input T+ T hysteresis voltage V . H Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environment. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V 5 V tolerant inputs for interfacing with 5 V logic CMOS low-power consumption Direct interface with TTL levels Unlimited input rise and fall times Inputs accept voltages up to 5.5 V Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 3. Applications Wave and pulse shapers for highly noisy environments Astable multivibrator Monostable multivibrator.74LVC132A NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC132AD 40 Cto +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74LVC132APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package 14 leads body SOT402-1 width 4.4 mm 74LVC132ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 5. Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 9 3A 3Y 8 & 8 10 3B 10 A 12 4A 12 4Y 11 Y 13 4B & 11 13 B mna212 mna246 001aac532 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LVC132A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 7 December 2011 2 of 16