74LV374PW,118 NXP

74LV374 Octal D-type ip-op positive edge-trigger 3-state Rev. 02 14 May 2009 Product data sheet 1. General description The 74LV374 is an octal D-type ip-op featuring separate D-type inputs for each ip-op and 3-state outputs for bus-oriented applications. A clock input (CP) and an output enable input (OE) are common to all ip-ops. The 74LV374 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC374 and 74HCT374. The eight ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the eight ip-ops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Common 3-state output enable input n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV374N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74LV374D - 40 C to +125 C SO20 plastic small outline package 20 leads body width 7.5 mm SOT163-1 74LV374DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LV374PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm74LV374 NXP Semiconductors Octal D-type ip-op positive edge-trigger 3-state 4. Functional diagram 1 EN 11 C1 11 3 2 1D CP 3 2 D0 Q0 4 5 4 5 D1 Q1 7 6 7 6 D2 Q2 8 9 8 9 D3 Q3 13 12 13 12 D4 Q4 14 15 14 15 D5 Q5 17 16 D6 Q6 17 16 18 19 D7 Q7 18 19 OE 1 mna891 mna196 Fig 1. Logic symbol Fig 2. IEC logic symbol 3 D0 Q0 2 4 D1 Q1 5 7 Q2 6 D2 Q3 8 D3 FF1 9 3-STATE to 13 D4 Q4 12 OUTPUTS FF8 14 D5 Q5 15 17 Q6 16 D6 18 D7 Q7 19 CP 11 1 OE mna892 Fig 3. Functional diagram 74LV374 2 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 14 May 2009 2 of 17