INTEGRATED CIRCUITS
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
Product specification 1998 Jun 10
Supersedes data of 1997 Mar 04
IC24 Data Handbook
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
74LV377
positive edge-trigger
FEATURES DESCRIPTION
The 74LV377 is a lowvoltage CMOS device and is pin and function
Optimized for Low Voltage applications: 1.0 to 3.6V
compatible with 74HC/HCT377.
Accepts TTL input levels between V = 2.7V and V = 3.6V
CC CC
The 74LV377 has eight edge-triggered, D-type flip-flops with
Typical V (output ground bounce) 0.8V @ V = 3.3V, individual D inputs and Q outputs. A common clock (CP) input loads
OLP CC
all flip-flops simultaneously when the data enable (E) is LOW. The
T = 25C
amb
state of each D input, one set-up time before the LOW-to-HIGH
Typical V (output V undershoot) 2V @ V = 3.3V,
OHV OH CC
clock transition, is transferred to the corresponding output (Q ) of
n
T = 25C
amb
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
Ideal for addressable register applications
Data enable for address and data synchronization applications
Eight positive-edge triggered D-type flip-flops
Output capability: standard
I category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T = 25C; t = t 2.5 ns
amb r f
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
t /t 13 ns
PHL PLH
CP to Q
C = 15pF
n L
VV = 3.3V33V
CC
f Maximum clock frequency 77 MHz
max
C Input capacitance 3.5 pF
I
C Power dissipation capacitance per flip-flop Notes 1 and 2 20 pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in W)
PD D
2 2
P = C V f (C V f ) where:
D PD CC i L CC o
f = input frequency in MHz; C = output load capacity in pF;
i L
f = output frequency in MHz; V = supply voltage in V;
o CC
2
(C V f ) = sum of the outputs.
L CC o
2. The condition is V = GND to V
I CC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL 40C to +125C 74LV377 N 74LV377 N SOT146-1
20-Pin Plastic SO 40C to +125C 74LV377 D 74LV377 D SOT163-1
20-Pin Plastic SSOP Type II 40C to +125C 74LV377 DB 74LV377 DB SOT339-1
20-Pin Plastic TSSOP Type I 40C to +125C 74LV377 PW 74LV377PW DH SOT360-1
PIN DESCRIPTION FUNCTION TABLE
PIN INPUTS OUTPUTS
SYMBOL FUNCTION
OPERAOPERATINGTING MODESMODES
NUMBER
CP E D Q
n n
1 E Data enable input (active-LOW)
Load 1 l h H
2, 5, 6, 9, 12,
Q to Q flip-flop outputs
Load 0 l l L
0 7
15, 16, 19
h X No change
3, 4, 7, 8, 13,
Hold (do nothing)
D to D Data inputs X H X No change
0 7
14, 17, 18
H = HIGH voltage level
10 GND Ground (0V)
h = HIGH voltage level one set-up time prior to the
Clock input LOW-to-HIGH CP transition
11 CP
(LOW-to-HIGH, edge-triggered) L = LOW voltage level
l = LOW voltage level one set-up time prior to the
20 V Positive supply voltage
CC
LOW-to-HIGH CP transition
= LOWtoHIGH CP transition
X = Dont care
2
1998 Jun 10 8531935 19545