74LV574DB,118 NXP

74LV574 Octal D-type ip-op; positive edge-trigger; 3-state Rev. 04 14 May 2009 Product data sheet 1. General description The 74LV574 is an octal D-type ipop featuring separate D-type inputs for each ip-op and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all ip-ops. It is a low-voltage Si-gate CMOS device and is pin and functionally compatible with the 74HC574 and 74HCT574. The eight ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the eight ip-ops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Common 3-state output enable input n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type Package number Temperature range Name Description Version 74LV574N - 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74LV574D - 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LV574DB - 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74LV574PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm74LV574 NXP Semiconductors Octal D-type ip-op; positive edge-trigger; 3-state 4. Functional diagram 11 C1 1 EN 11 2 19 CP 1D 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 OE 1 mna798 mna446 Fig 1. Logic symbol Fig 2. IEC logic symbol 2 D0 Q0 19 D1 3 Q1 18 D2 4 Q2 17 5 D3 FF1 Q3 16 3-STATE to 6 D4 Q4 15 OUTPUTS FF8 Q5 7 D5 14 8 D6 Q6 13 9 D7 Q7 12 CP 11 1 OE mna800 Fig 3. Functional diagram 74LV574_4 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 14 May 2009 2 of 17