74LV595D,112 Nexperia

74LV595 8-bit serial-in/serial-out or parallel-out shift register 3-state Rev. 5 29 September 2021 Product data sheet 1. General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb Has a shift register with direct clear Output capability: Parallel outputs bus driver Serial output standard Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to 85 C and -40 C to 125 C 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74LV595 8-bit serial-in/serial-out or parallel-out shift register 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV595D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV595PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 5. Functional diagram 13 EN3 12 C2 11 12 10 SHCP STCP R SRG8 11 9 C1/ Q7S 15 Q0 14 15 1D 2D 3 1 Q1 1 2 Q2 2 14 3 DS Q3 3 4 Q4 4 5 Q5 5 6 Q6 6 7 Q7 7 MR OE 9 10 13 mna552 mna553 Fig. 1. Logic symbol Fig. 2. Logic symbol (IEEE/IEC) 14 DS 11 SHCP 8-STAGE SHIFT REGISTER 10 MR Q7S 9 12 STCP 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 mna554 Fig. 3. Functional diagram 74LV595 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 29 September 2021 2 / 17